Using std_logic_vector

Some solutions have declared the shift register as four separate std_logic signals. While this works, it is more verbose than using a single 4-bit std_logic_vector. The last section of Lecture 1 (Introduction to Logic Synthesis with VHDL) describes how you can shift a bit into a vector. For example:

signal databits, databits_next : std_logic_vector(3 downto 0) ;
...
databits_next <= ... when ... else
             '0' & databits(3 downto 1) ;
databits <= databits_next when rising_edge(sclk) ;

will shift the bits in the 'databits' register when the first condition is not true.

Registers

Your solution should require only three registers and the associated combinational logic that sets their next values:

• a 4-bit shift register containing the values of the bits remaining to be sent
• a 3-bit counter for the number of bits left to send
• a flip-flop that registers the ss_n output

MOSI output

As explained in a discussion forum posting, the least-significant bit of the shift register (`databits' above) is already registered by sclk and can be connected directly to the mosi output.